Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-03-05
1998-09-29
Le, Vu A.
Static information storage and retrieval
Addressing
Sync/clocking
365203, 365233, G11C 700
Patent
active
058154647
ABSTRACT:
An address transition detection circuit having a number of cells supplied with respective address signals and outputs connected in a wired NOR configuration to generate a pulse signal on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage for generating an end-of-transition signal with a predetermined delay following reception of the pulse signal; and an output stage connected to the cells and to the monostable stage, which generates the first switching edge of the address transition signal on receiving the pulse signal, and the second switching edge on receiving the end-of-transition signal. The monostable stage presents a compensating structure for maintaining the delay in the switching of the end-of-transition signal despite variations in temperature and supply voltage.
REFERENCES:
patent: 5264737 (1993-11-01), Oikawa
patent: 5374894 (1994-12-01), Fong
patent: 5493538 (1996-02-01), Bergman
Golla Carla Maria
Zammattio Matteo
Zanardi Stefano
Le Vu A.
SGS-Italy Microelectronics S.r.l.
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