Static information storage and retrieval – Addressing – Sync/clocking
Patent
1993-10-29
1995-08-01
Yoo, Do Hyun
Static information storage and retrieval
Addressing
Sync/clocking
36518907, 365194, 326 93, 327143, 327175, 327227, G11C 800
Patent
active
054385504
ABSTRACT:
An ATD circuit of a semiconductor memory device includes a variable delay line for delaying an address signal, a logic comparator for comparing the logic of the address signal with that of the address signal delayed by the variable delay line to generate an ATD pulse signal having a constant width at the rising and falling edges of the address signal, and a power supply voltage detector for detecting a voltage level of the power supply voltage to adjust the length of the variable delay line according to the voltage level, so that the pulse width of the ATD pulse signal for controlling precharge and voltage equalization of a bit line and operation of a sense amplifier is constantly maintained independently of the variation of a power supply voltage to thus improve access speed of the semiconductor memory device.
REFERENCES:
patent: 5025422 (1991-06-01), Moriwaki et al.
patent: 5124584 (1992-06-01), McClure
patent: 5159574 (1992-10-01), Kim et al.
patent: 5264737 (1993-11-01), Oikawa
Hyundai Electronics Industries Co,. Ltd.
Yoo Do Hyun
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