Address transition detecting circuit

Details Address transition detecting circuit Address transition detecting circuit

2001-12-07

2003-10-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S189050

Reexamination Certificate

active

06639870

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to an address transition detecting circuit. More particularly, the invention is concerned with an address transition detecting circuit capable of preventing generation of unnecessary address transition detection signal pulses when glitch is generated and thus stably driving semiconductor chips even at a high power supply voltage, by including a control means for controlling charge/discharge of a given portion of the address transition detecting circuit and a noise removing circuit for removing the address transition detection signal included in the noise at an output terminal of the address transition detecting circuit, in order to remove noises of the address transition detection signal generated by a glitch signal included in a given signal applied to an input terminal of the address transition detecting circuit.
2. Description of the Prior Art
The intensity of semiconductor memory devices becomes higher and its access speed to data becomes also higher. This results from that the processing speed of a microprocessor is further higher. The semiconductor memory devices adopt various technologies for higher operation. One of them is an address transition detecting circuit (hereinafter called “ATD”).
An operation principle of the ATD will be shortly described as follows.
The ATD detects an address transition inputted outside the chip to internally generate a pulse and internal circuits are synchronized to this pulse to allow a higher operation of the chip.
Referring now to
FIG. 1
, there is shown a detailed circuit diagram of a conventional ATD.
The ATD includes an address pad
100
for receiving a drain signal ADD as an input to output an address pad signal APAD, an address buffer
101
for internally buffering the address pad signal APAD through the address pad
100
, a first pulse detecting unit
102
for detecting a first transition of an output signal AF of the address buffer
101
, a second pulse detecting unit
103
for detecting a second transition of an output signal AF of the address buffer
101
, a voltage fall unit
105
for falling the power supply voltage applied to the first pulse detecting unit
102
and the second pulse detecting unit
103
to a given voltage, and an output unit
104
for inverting the output signals of the first pulse detecting unit
102
and the second pulse detecting unit
103
.
The first pulse detecting unit
102
includes a third inverting means
1
connected to an output terminal of the first inverting means I
1
for inverting the address buffer signal AF, for inverting an output signal of the first inverting means I
1
; a first buffering means
3
connected to an output terminal of the third inverting means
1
, for stabilizing an output signal of the third inverting means
1
to a given potential; a first delay means
5
connected between a first node Q
1
connected to an output terminal of the third inverting means
1
and a ground terminal Vss; and a fifth inverting means
7
connected between the power supply terminal Vcc and the ground terminal Vss, for inverting the potential of the first node Q
1
.
Also, the second pulse detecting unit
103
includes a second inverting means I
2
for inverting an output signal of the first inverting means I
1
; a fourth inverting means
2
for inverting an output signal of the second inverting means
12
; a second buffering means
4
for stabilizing an output signal of the fourth inverting means
2
to a given potential; a second delay means
6
connected between the second node Q
2
connected to an output terminal of the fourth inverting means
2
and the ground terminal Vss; and a sixth inverting means
8
connected between the power supply terminal Vcc and the ground terminal Vss, for inverting the potential of the second node Q
2
.
The output unit
104
includes a seventh inverting means I
3
for inverting one of the output signals from the output terminal of the first pulse detecting unit
102
or the second pulse detecting unit
103
to output an address transition detection signal ATDout.
The voltage fall unit
105
includes a first PMOS transistor P
1
and a first resistor R
1
, which are in parallel connected between the power supply terminal Vcc and the second resistor R
2
. The first PMOS transistor P
1
is driven by the first signal DPD that is generated in an external signal generating circuit.
The third inverting means
1
includes the second PMOS transistor P
2
and the first NMOS transistor N
1
, which are serially connected between the second resistor R
2
and the ground terminal Vss. The fourth inverting means
2
includes the third PMOS transistor P
3
and the second NMOS transistor N
2
, which are serially connected between the second resistor R
2
and the ground terminal Vss.
The first buffering means
3
includes a first capacitor C
1
connected between the power supply terminal Vcc and the first node Q
1
, and a second capacitor C
2
connected between the ground terminal Vss and the first node Q
1
. The second buffering means
4
includes a third capacitor C
3
connected between the power supply terminal Vcc and the second node Q
2
, and a fourth capacitor C
4
connected between the ground terminal Vss and the second node Q
3
.
The first delay means
5
includes the fourth PMOS transistor P
4
and the fifth capacitor C
5
, which are connected between the first node Q
1
and the ground terminal Vss. The second delay means
6
includes the fifth PMOS transistor P
5
and the sixth capacitor C
6
, which are connected between the second node Q
2
and the ground terminal Vss. The fourth PMOS transistor P
4
and the fifth PMOS transistor P
5
are driven by a second signal OPC generated in an external signal generating circuit.
The fifth inverting means
7
includes a sixth PMOS transistor P
6
connected between the power supply terminal Vcc and the ground terminal Vss and driven depending on an output signal of the first inverting means I
1
; a seventh PMOS transistor P
7
driven by the potential of the first node Q
1
, for inverting the potential of the first node Q
1
; and a fourth NMOS transistor N
4
driven depending on the output signals of the third NMOS transistor N
3
and the second inverting means I
2
.
The sixth inverting means
8
includes an eighth PMOS transistor P
8
connected between the power supply terminal Vcc and the ground terminal Vss and driven depending on an output signal of the second inverting means
12
; a ninth PMOS transistor P
9
and a fifth NMOS transistor N
5
driven by the potential of the second node Q
2
, for inverting the potential of the second node Q
2
; and a sixth NMOS transistor N
6
driven by an output signal of the first inverting means I
1
.
The ATD circuit constructed as mentioned above detects that the first pulse detecting unit
102
transits the output signal AF of the address buffer
101
from LOW to HIGH, and the second pulse detecting unit
103
transits the output signal AF of the address buffer
101
from HIGH to LOW.
It will be explained in conjunction with the operational timing in FIG.
4
. The address signal ADD inputted to the address pad
100
pass through the address buffer
101
and then outputs the address buffer signal AF having the same phase to the address signal ADD inputted to the address pad
100
to apply it to the first pulse detecting unit
102
and the second pulse detecting unit
103
.
For example, if the address signal ADD inputted to the address pad
100
is transited from a HIGH state to a LOW state during the period from “T1” time to “T2” time, the address transition detection signal ATDout the initial state of which is HIGH is transited to a LOW state and is then transited to a HIGH state during the period from “T2” time to “T3” time when the potential on the second node Q
2
is transited from a LOW state to a HIGH state.
In more detail, the address buffer
101
outputs the address buffer signal AF having the same phase to the address pad signal APAD during the period from “T1” time to “T2” time. The address buffer sign

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