Static information storage and retrieval – Addressing – Sync/clocking
Patent
1992-12-08
1994-05-17
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Sync/clocking
365 49, 365154, 365190, 36523008, G11C 700, G11C 800
Patent
active
053134362
ABSTRACT:
An address transition detecting circuit which couples to a word line and an address signal line, which address signal line receives an address signal, is disclosed. The address transition detecting circuit has a word line control circuit and an address signal input circuit. The word line control circuit couples to the word line and discharges the word line. The address signal input circuit couples to the word line, the address signal line and the word line control circuit and stores an address data in response to the address signal. The address signal input circuit outputs an address transition signal to the word line in response to the address signal and the stored address data.
REFERENCES:
patent: 4833643 (1989-05-01), Hori
patent: 5226005 (1993-07-01), Lee et al.
"High-Speed IC Memory", Electronic Engineering vol. 28, No. 9, Aug. 8, 1986, pp. 34-41.
"On-Chip Cache Memory for Microprocessor (an Application of CAM)", The Institute of Electronics Communication Engineerings Technical Report, vol. 86, No. 191, SSD86-95, pp. 25-30.
LaRoche Eugene R.
Mai Son
OKI Electric Industry Co., Ltd.
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