Address transition detect control circuit for self timed...

Details Address transition detect control circuit for self timed... Address transition detect control circuit for self timed...

2005-12-27

2005-12-27

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S189080, C365S189090, C365S196000, C365S203000, C365S205000, C365S207000, C365S230080

Reexamination Certificate

active

06980481

ABSTRACT:
A memory circuit generally comprising a bit cell, a sense amplifier, and a control circuit. The bit cell may be configured to generate a bit signal. The sense amplifier may be configured to generate a reset signal in response to sensing the bit signal. The control circuit may be configured to (i) set a control latch in response to a detection signal and (ii) reset the control latch in response to the reset signal, wherein the control latch is set while both the detection signal and the reset signal are in an asserted state.

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