Address transistion detect timing architecture for a simultaneou

Details Address transistion detect timing architecture for a simultaneou Address transistion detect timing architecture for a simultaneou

1999-10-19

2000-08-29

Phan, Trong

Static information storage and retrieval

Floating gate

Particular connection

36518533, 365233, 3652335, 365194, G11C 1604, G11C 800

Patent

active

061117870

ABSTRACT:
An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.

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