Address transformation circuit arrangement

Details Address transformation circuit arrangement Address transformation circuit arrangement

1986-10-03

1989-03-07

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1206, G06F 1210

Patent

active

048112127

ABSTRACT:
Two circuit arrangements are described for transforming 2.sup.n global addresses used in a control engineering system having several local units into 2.sup.m local addresses used in one of the units of the system. One of these contains several memories in which subfunctions resulting from a splitting of the transformation function conveying the transformation are stored. The other circuit arrangement contains a single memory which accepts all subfunctions. The transformation function is split into the subfunctions in such a manner that an optimum compromise is achieved between the storage space required for storing the subfunctions and the time required for the transformation.

REFERENCES:
patent: 3813652 (1974-05-01), Elmer et al.
patent: 4156925 (1979-05-01), Tutt et al.
patent: 4279014 (1981-07-01), Cassonnet et al.
"Memory Addressing Scheme for Loosely Coupled Processors", Marton et al, IBM Tech Disc. Bull., vol. 22, No. 7, pp. 2883-2884 (Dec. 1979).

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