Address tenure control for cache management wherein bus master a

Details Address tenure control for cache management wherein bus master a Address tenure control for cache management wherein bus master a

1995-04-28

1998-09-22

Asta, Frank J.

Boots, shoes, and leggings

364DIG1, 395445, 395468, 395473, 395481, 395496, G06F 1300

Patent

active

058128158

ABSTRACT:
Systems and methods which provide a minimized address tenure to create more efficient memory transactions where the address is not needed for longer than the initial clock cycle in which it is used are described. The exceptions, for example, wherein the address is needed later during the transaction to perform a cache operation, are handled by reasserting the address using the cache controller. In this way, memory transactions are made more efficient but without the use of external latches conventionally used to preserve the deasserted address.

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