Address system for bus interconnected computer system

Details Address system for bus interconnected computer system Address system for bus interconnected computer system

1979-03-02

1981-02-03

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 704, G06F 1300

Patent

active

042492408

ABSTRACT:
A computer system employs a CPU interconnected to a number of devices and terminals over a common bus. Each device has a different address assigned to it and a message from one device to another, over the bus, is prefixed with the receiving device's address. To simplify the hardware of input/output devices connected to the system all such devices have an abbreviated address and a prefix common to the class. A decoder detects when this prefix is transmitted on the address bus and sends a signal over a line that connects only to these devices. When the devices receive a signal on this line they examine the abbreviated portion of the address and are activated when coincidence is detected.

REFERENCES:
patent: 3919693 (1975-11-01), Anderson
patent: 4001790 (1977-01-01), Barlow
patent: 4024505 (1977-05-01), Sperling

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