Address strobe signal generator for memory device

Details Address strobe signal generator for memory device Address strobe signal generator for memory device

1999-10-26

2002-03-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S230080

Reexamination Certificate

active

06356502

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from a Korean Patent Application No. 1998-45294, filed Oct. 28, 1998, which is incorporated herein by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memories and in particular to optimizing address input timing in memory devices.
Memory circuits are made up of a large number of memory cells located at the intersection of word lines (or rows) and bit lines (or columns). The memory cells are typically arranged in separate arrays with separate row and column decoders that decode the address of a selected memory cell.
FIG. 1
shows a simplified example of a prior art random access memory. In this typical prior art example, the memory arrays
100
are stacked on either sides of the global column decoder
102
. Sense amplifiers
104
are disposed in between the memory arrays
100
, and are typically shared by two adjacent memory arrays
100
. Power is supplied to the sense amplifiers
104
by power buses
110
that branch off a wide metal bus extending from the power pad
112
down the side of the array. A row decoder
106
is disposed at the end of each memory array
100
.
One common type of memory cell is the dynamic random access memory (DRAM).
FIG. 2
shows a typical array of memory cells for a DRAM. Memory cell array
200
includes an access transistor
202
that connects a storage capacitor
204
to a bit line. A word line
206
within a given array connects to the gate terminals of access transistors of a plurality of memory cells
200
. When a particular word line
206
i
is selected, all access transistors
202
connected to the word line turn on, allowing charge sharing to occur between the bit line parasitic capacitance
210
and the memory cell storage capacitor
204
. A sense amplifier (not shown) detects the increase or decrease in bit line voltage from the memory cell and drives the complementary bit lines to full logic levels, e.g., V
SS
corresponding to a logical “0” and V
DD
corresponding to a logical “1”, depending on the original voltage of stored in the memory cell. A selected column (i.e., bit line) decoder then connects a selected pair of bit lines to the I/O lines as described in connection with FIG.
1
.
To select memory cells, row and column addresses are applied to the memory device, which buffers and decodes the addresses.
FIG. 3
shows a typical prior art address decoding apparatus. The apparatus
300
generally contains a buffer array
320
having a plurality of address buffers
320
1
-
320
n
coupled to an address decoder
340
and a buffer controller
310
coupled to the address buffers
320
1
-
320
n
by a signal line
360
. The address buffers
320
1
-
320
n
receive address signals values via address lines
350
. A buffer controller
310
generates an address strobe signal on line
360
that strobes the address into the address buffers
320
1
-
320
n
. Outputs of the buffers
320
1
-
320
n
are then applied to an address decoder
340
. Controlling the timing of the decode operation is critical since address decoder
340
must receive all outputs of buffers
320
1
-
320
n
before it can validly decode the address signal. This is because, due to the varying distances between the outputs of buffers
320
1
-
320
n
and the inputs of address decoder
340
, the latched address signals at outputs of buffers
320
arrive at the inputs of decoder with different RC delays. Thus, address decoder
340
should not be enabled until the circuit ensures that all address signals have arrived at the inputs of decoder
340
.
The prior art apparatus of
FIG. 3
compensates for the varying RC delays by delaying an enable or strobe signal sent from the buffer controller to the address decoder, e.g. with a chain of inverters
370
. The number and size of the inverters is carefully chosen so that the delay imposed by inverter chain
370
is long enough to ensure that enough time lapses before the output of the outermost buffer
320
1
arrives at the input of decoder
340
. That is, the decoder enable signal is a delayed version of the address strobe signal, wherein the delay is equal to the sum of RC delay of interconnect line
360
, plus a delay through address buffer
320
1
, plus the RC delay through the longest interconnect line, plus a small margin. Consequently, in the prior art, the delay in the inverters is chosen to be equal to an upper limit of the known range of delays. In other words, inverter chain
370
was designed to apply a “worst case” delay to the address strobe sent to address decoder
340
. The design for the worst case delay unnecessarily slows down the faster memory devices.
Thus, there is a need in the art for an address-decoding scheme that optimizes the speed of address decoding.
SUMMARY OF THE INVENTION
The disadvantages associated with the prior art are overcome by the present invention of an apparatus and method for decoding address signals.
The apparatus generally comprises an address buffer array, a first control signal generator coupled to the address buffer array, an address decoder coupled to the address buffer array and a second control signal generator coupled to the address decoder and the first control signal generator. The address buffer array buffers address signals in response to a first control signal from the first control signal generator. The second control signal generator generates a second control signal in response to the first control signal. The address decoder decodes the buffered address signals in response to the second control signal. To accurately time the arrival of the second control signal and the buffered address signals at the decoder, the second control signal generator has one or more signal transfer characteristics in common with one or more of the address buffers. In a specific embodiment, the second control signal generator has a longer signal transfer delay than any address buffer in the address buffer array. For example, the second control signal generator may be connected to the first control signal generator by a signal path that is longer than a longest signal path connecting one of the address buffers with the first control signal generator. The second control signal generator may comprise a circuit substantially equivalent to each address buffer in the address buffer array. Furthermore input and output lines connected to the circuit may be substantially equivalent to input and output lines connected to an outmost address buffer located adjacent to the second control signal generator.
The method for decoding address signals generally comprises buffering address signals in a buffer array in response to the first control signal. The second control signal generator generates the second control signal by delaying the first control signal using signal transferring characteristics of the buffer array. Thus, the second control signal determines an input timing margin of the address decoder. The address decoder then decodes the buffered address signals in response to the second control signal.
The present invention ensures that, for a given memory device, the delay in decoding the address closely matches inherent delays in the buffer array. Thus, memory devices having buffers with shorter than average inherent delays will not be slowed down unnecessarily.


REFERENCES:
patent: 4905201 (1990-02-01), Ohira et al.
patent: 4951258 (1990-08-01), Uehara
patent: 5546352 (1996-08-01), Sato et al.
patent: 5732040 (1998-03-01), Yabe
patent: 5973987 (1999-10-01), Akai et al.
patent: 6064618 (2000-05-01), Kuriyama et al.
patent: 0 135 940 (1985-03-01), None
patent: 0 180 895 (1986-05-01), None
patent: 0 553 547 (1993-08-01), None
patent: 1996-005293 (2001-03-01), None

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