Address strobe recognition in a memory device

Details Address strobe recognition in a memory device Address strobe recognition in a memory device

1997-07-09

1998-11-03

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 365239, G11C 800

Patent

active

058319310

ABSTRACT:
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.

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