Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-04-03
1999-12-21
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
365203, 365205, 36518908, G11C 700
Patent
active
060058269
ABSTRACT:
An address signal transition detecting apparatus includes an address transition detecting circuit for detecting transitions in address signals, accordingly generating address transition detection signals and summing the address transition detection signals to generate an address transition detection sum signal ATDSUM, respectively outputting a first pulse signal YE for activating a column address decoder, a second pulse signal P for activating a precharger and a third pulse signal SE for activating a sense amplifier in accordance with an address transition detecting sum signal ATDSUM, and once again outputting another first pulse signal YE for activating the column address decoder in response to a fourth pulse signal YE2 generated in accordance with the address transition detection sum signal ATDSUM and the first pulse signal YE. The apparatus enables accurately reading a data signal on a data line by twice generating the first pulse signal YE that serves to activate the column address decoder, whereby the sense amplifier is able to sense a data signal in an improved manner.
REFERENCES:
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 4894803 (1990-01-01), Aizaki
patent: 5264737 (1993-11-01), Abe
patent: 5313434 (1994-05-01), Abe
patent: 5335207 (1994-08-01), Takamoto
patent: 5694369 (1997-12-01), Abe
Ahn Jin-Hong
Yoon Oh-Sang
Ho Hoai V.
LG Semicon Co. Ltd.
Nelms David
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