Address selective emulation routine pointer address mapping syst

Details Address selective emulation routine pointer address mapping syst Address selective emulation routine pointer address mapping syst

1993-09-20

1995-02-21

Lall, Parshotam S.

Boots, shoes, and leggings

395425, 364DIG1, 364DIG2, G06F 1210

Patent

active

053924088

ABSTRACT:
An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output on the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an instruction mapping system.

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