Address selection device

Details Address selection device Address selection device

1980-09-03

1984-08-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307571, 307582, H03K 301, H03K 17687, H03K 19094

Patent

active

044672250

ABSTRACT:
An address selection device comprising an address buffer for receiving an address selection signal to produce an output signal which is complementary to the address selection signal; and a decoder circuit for decoding the address selection signal which includes a plurality of MOS transistors connected in parallel with one another and for receiving at their gates corresponding address bit signals of the address selection signal, a MOS transistor as a load resistor connected in series with said plurality of MOS transistors, and a MOS transistor connected between the load resistor MOS transistor and a power source terminal for operating a power source switch and for receiving at the gate a specified bit signal of the complementary signal applied from the address buffer.

REFERENCES:
patent: Re30744 (1981-09-01), Cole et al.
patent: 3653034 (1972-03-01), Regitz
patent: 3825888 (1974-07-01), Kawagoe
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4027174 (1977-05-01), Ogata
patent: 4048632 (1977-09-01), Spence
patent: 4096584 (1978-06-01), Owen et al.
Salsbury, et al., High Performance MOS EPROMs Using a Stacked-Gate Cell, 1977 IEEE International Solid-State Circuits Conference, 186-187 (Feb. 18, 1977).

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