Address selection circuitry and method using single analog...

Coded data generation or conversion – Analog to or from digital conversion – Multiplex

Reexamination Certificate

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Details

C341S118000

Reexamination Certificate

active

06255973

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to address selection circuitry and methods and more particularly to circuitry and methods adapted to provide an address for each one of a plurality of addressable integrated circuits.
As is known in the art, many systems use addressable integrated circuits. One such system is a so-called System Management (SM) bus system and is shown in FIG.
1
. Here, the SM bus has two lines; line SDA is for data and addresses and line SCL is for clock pulses. As shown, each one of the addressable Application Specific Integrated Circuits (ASICS) used in the SM system have a single pin ADDR to receive the address to be selected, and stored in, such one of the ASICs. The single pin ADDR allows the designer to tie the pin to one of three signal levels, i.e., a high voltage signal level, a low voltage signal level, or an open circuit, or “floating” voltage signal level. More particularly, each one of the levels corresponds to a different two bit word used in the address of the ASIC. Still more particularly, during an initial address select mode, the signal level on the ADDR pin is converted into one of three possible portions of the address for the ASIC. That is, a slave address register (
FIG. 2
) is provided in each ASIC. Each register stores, for example, a seven bit address. The five most significant bits are previously stored in the address register. However, the last two bits are derived from the voltage level on the ADDR pin. Thus, here for example, at power-on the level on the ADDR pin is passed through a decoder. Here, for example, if the level on the ADDR pin is high, the decoder produces a two bit word
00
. It the level on the ADDR pin is low, the decoder produces a two bit word 11. Finally, if there is an open circuit on the ADDR pin, the decoder produces a two bit word
01
. At power-on the two bit word produced by the decoder is stored as the two least significant bits in the slave address register. The contents of the slave address register are then used as the address for the ASIC during the normal mode. That is, during the normal operating mode, the here seven bit address of the ASIC, which is stored in the slave address decoder, is fed to a serial interface (which includes a comparator) of the ASIC. Thus, if the address on the SDA line is the same as the address stored in the address register, comparator indicates to the ASIC that it is the ASIC being addressed.
While such an address select system is useful in some applications if more than three addresses are required additional ADDR pins would be needed for each ASIC to accommodate the three level signal (i.e., a high level voltage, a low level voltage, or an open circuit condition). That is, one of these three conditions would be placed on a corresponding one of the additional ADDR pins of the ASIC.
SUMMARY OF THE INVENTION
In accordance with the invention, an address select circuit for an addressable integrated circuit is provided. The address select circuit includes a signal source and a circuit for coding such signal source into a corresponding signal at a pin of the integrated circuit. The signal at the pin has a selected one of more than three predetermined signal levels. The integrated circuit includes a converter, having an input adapted for coupling to the pin, for converting the coded signal level into a address signal for such integrated circuit. The integrated circuit includes a register for storing the address signal for such integrated circuit.
With such circuitry the single pin of the integrated circuit can be fed with more than three signal levels using only a single ADDR pin, each level corresponding to a selected address for the integrated circuit. The converter of the integrated circuit converts the signal level into the desired address for the integrated circuit for use during a subsequent normal operating mode. The converter may be an analog to digital converter already available in the integrated circuit for processing other analog signals, such as, for example, the temperature of the integrated circuit or an external temperature.
In accordance with one embodiment of the invention, an address select circuit is provided for providing an address for an integrated circuit. The address select circuit includes a signal source. A circuit is provided for coding such signal source into a corresponding signal at a pin of the integrated circuit, such signal having a selected one of more than three predetermined signal levels. The integrated circuit includes a converter for converting such selected one of the signal levels into a address signal for such integrated circuit during an initial address select mode and for providing conversion of a second signal in the integrated circuit for use by such integrated circuit in processing the second signal during a subsequent normal operating mode.
In one embodiment of the invention, the converter is an analog to digital converter.
In one embodiment of the invention, the second signal is indicative of temperature.
In accordance with still another embodiment of the invention, a system is provided having a plurality of address select circuits, each one thereof being coupled to a corresponding one of a corresponding plurality of addressable integrated circuit. Each one of such integrated circuits has an address select pin adapted to receive an address select signal from the corresponding one of the address select circuits. The address select signal is indicative of an address for such one of the plurality of addressable integrated circuits. Each one of such address circuits includes a signal source and a circuit for coding such signal source into a corresponding signal at a pin of the integrated circuit. The signal has a selected one of more than three predetermined signal levels. The integrated circuit includes a converter for converting such selected one of the signal levels into a address signal for such one of the integrated circuits. The integrated circuit also includes a register for storing the address signal for such one of the integrated circuits.
In accordance with still another embodiment of the invention, a method is for providing an address for an addressable integrated circuit. The method includes providing a signal source and coding such signal source into a corresponding signal at a pin of the integrated circuit, such signal being coded with a selected one of more than three predetermined signal levels. The selected one of the signal levels is converted into a address signal for such integrated circuit. The address signal for such integrated circuit is stored in the integrated circuit.
In accordance with yet another embodiment of the invention, a method is provided wherein a plurality of address select circuits are coupled to a corresponding one of a corresponding plurality of addressable integrated circuit. Each one of such integrated circuits has an address select pin adapted to receive an address select signal from the corresponding one of the address select circuits. The address select signal is indicative of an address for such one of the plurality of addressable integrated circuits. The method includes providing a signal source and coding such signal source into a corresponding signal at a pin of the integrated circuit. The signal is coded with a selected one of more than three predetermined signal levels. The selected one of the signal levels is converted into a address signal for such one of the integrated circuits. The address signal for such one of the integrated circuits is stored in the integrated circuit.
In accordance with one embodiment, converting such selected one of the signal levels into a address signal for such one of the integrated circuits takes place during an initial address select mode and a second signal in the integrated circuit is converted for use by such integrated circuit in processing the second signal during a subsequent normal operating mode.


REFERENCES:
patent: 5784020 (1998-07-01), Inoue

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