Address range bank decoding for DRAM

Details Address range bank decoding for DRAM Address range bank decoding for DRAM

1994-09-08

1995-09-19

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

3652385, G11C 1300

Patent

active

054522579

ABSTRACT:
A method of decoding a memory bank in a DRAM controller system is described that includes obtaining an access address of the bank, defining a begin address of the bank, defining an end address of the bank, and comparing the begin and the end addresses with the access address. A DRAM controller system bank decoding circuit is also disclosed comprising a first comparator for the access address of the bank and the end address of the bank, with an output of the first comparator, corresponding to the access address being less than the end address, connected to a first input of an AND logic gate, a second comparator comparing the access address with the begin address of the bank, with an output of the second comparator, corresponding to the access address being larger than or equal to the begin address, connected to a second input of an AND logic gate.

REFERENCES:
patent: 5134589 (1992-07-01), Hamano

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