Address prediction to avoid address generation interlocks in com

Details Address prediction to avoid address generation interlocks in com Address prediction to avoid address generation interlocks in com

1992-10-23

1995-08-15

Robertson, David L.

395410, 395414, 39542104, G06F 1200

Patent

active

054427673

ABSTRACT:
A computer system predicts an address required to execute a current iteration of a program instruction based on addresses required to execute previous iterations of the same program instruction. The system stores an address required to execute the previous iteration of the program instruction, and determines differences between addresses required to execute successive iterations of the program instruction prior to the current iteration. The system also determines and stores a current value of a delta, and predicts the address required to execute the current iteration of the program instruction based on the address required to execute the previous iteration of the program instruction plus the current value of the delta. The system sets the delta at one time equal to a difference between two addresses required to execute two successive iterations of the program instruction and updates delta when two actual differences between three addresses required to execute three successive iterations of the program instruction are equal to each other and different than delta. Thus, the system predicts constantly spaced addresses unless two successive addresses have a different spacing than the previous address. This is particularly advantageous when the program instruction adds data stored as elements of rows of one or more matrices. While the prediction will be incorrect for the first element in each row (and the first two elements in the first row) of each matrix, the prediction will be correct for all other elements in the rows, even if the inter-element spacings in rows of the different matrices are different than each other. For each of some predictions for successive iterations of the program instruction, the system negates the current value of the delta, whereby the predictions alternate between two addresses for multiple iterations of the program instruction.

REFERENCES:
patent: 4583162 (1986-04-01), Prill
patent: 4594659 (1986-06-01), Guenthner et al.
patent: 4729092 (1988-03-01), Lupton
patent: 4760520 (1988-07-01), Shintani et al.
patent: 4853840 (1989-08-01), Shibuya
patent: 4888689 (1989-12-01), Taylor et al.
patent: 4984772 (1990-01-01), Langendorf
patent: 4991080 (1991-02-01), Emma et al.
patent: 5007011 (1991-04-01), Murayama
patent: 5121473 (1992-06-01), Hodges
INSPEC-IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Comput. Soc. Press, pp. 408-412, 1990, by Hua et al.
IBM TDB vol. 24, No. 1A, Jun. 1981, "Address Generate Interlock Avoidance For Branch Instructions In A Branch-History-Table Processor", by Driscoll, et al.
IBM TDB vol. 25 No. 1, Jun. 1982, "Generalized History Table For Branch Prediction", by Losq.
IBM TDB vol. 26, No. 4, Sep., 1983, "Elimination Of Address Generation Interlocks On Sequences Of Load Instructions", by Meltzer.

Affiliated with

Also associated with

Rating

Address prediction to avoid address generation interlocks in com does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address prediction to avoid address generation interlocks in com, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address prediction to avoid address generation interlocks in com will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2190380