Address pointer generating and using a coincidence signal in a s

Details Address pointer generating and using a coincidence signal in a s Address pointer generating and using a coincidence signal in a s

1994-09-19

1995-09-05

Nelms, David C.

Static information storage and retrieval

Addressing

Counting

365221, 365233, 365239, 365240, G11C 800

Patent

active

054485304

ABSTRACT:
A counter counts clock signals. When a count thereof coincides with the number of rows or columns in a memory cell array, a row or column count coincidence signal is generated and applied to a shift input of a row or column address pointer formed of shift registers. The row or column address pointer is responsive to the clock signals to sequentially shift the count coincidence signal applied to the shift input, so that row or column selecting lines in the memory cell array are sequentially set in the selected state. Since the outputs at final stages in the row and column address pointers are not fed back to the inputs at the first stage thereof, signal delay in a feed back path is not caused, and thus operations for selecting rows and columns are performed at high speed. Also, respective shift register stages in the row and column address pointers have the same construction, and thus regularity thereof is maintained.

REFERENCES:
patent: 4395764 (1983-07-01), Matsue
patent: 4945518 (1990-07-01), Muramatsu et al.
patent: 4947373 (1990-08-01), Yamaguchi et al.
patent: 5144525 (1992-09-01), Saxe et al.
patent: 5146577 (1992-09-01), Babin
patent: 5146577 (1992-09-01), Babin
patent: 5206834 (1993-04-01), Okitaka et al.

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