Address pattern generator for testing a memory

Details Address pattern generator for testing a memory Address pattern generator for testing a memory

1979-10-10

1981-11-10

Atkinson, Charles E.

Excavating

324 73R, 364900, 371 21, G01R 3128

Patent

active

043002340

ABSTRACT:
An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.

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patent: 4079453 (1978-03-01), Dahl
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