1993-03-05
1995-12-05
Beausoliel, Jr., Robert W.
Excavating
371 211, 371 27, G06F 1100
Patent
active
054736161
ABSTRACT:
An address pattern generator for generating regular addresses in a freely set aside area of the memory cell to be tested. The arrangement of the column address generator is structured the same as that of the row address generator wherein both the column address generator and the row address generator receive an add signal from a control circuit, address values from first and second maximum value registers and address values from first and second initial value registers. The column address generator has a comparator which compares an address to be supplied to the memory to be tested with the address value output from the first maximum value register and a selection circuit which selects address to be supplied to the memory using a signal output from the comparator.
REFERENCES:
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 4051460 (1977-09-01), Yamada
patent: 4293950 (1981-10-01), Shimizu
patent: 4300234 (1981-11-01), Maruyama
patent: 4384348 (1983-05-01), Nozaki
Takeshita Hiroki
Tsutsui Yasumitsu
Ando Electric Co. Ltd.
Beausoliel, Jr. Robert W.
Snyder Glenn
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