Address parity check system

Details Address parity check system Address parity check system

1979-07-09

1981-06-02

Smith, Jerry

Excavating

G06F 1110

Patent

active

042715210

ABSTRACT:
Apparatus and method for detecting errors in addressing as well as transfer and storage of data. Both odd and even parity are alternately assigned to data words as a function of the memory address where a particular data word is stored. A parity error on reading occurs when either an error has occurred in the data word itself or when the memory has been incorrectly addressed.

REFERENCES:
patent: 3585378 (1971-05-01), Bouricius et al.
patent: 3599146 (1971-08-01), Weisbecker
patent: 3789204 (1974-01-01), Barlow
patent: 3914741 (1975-10-01), Bonser et al.
patent: 3992696 (1976-11-01), Fergeson
patent: 4020459 (1977-04-01), Coomer

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