Address pairing apparatus for a control store of a data processi

Details Address pairing apparatus for a control store of a data processi Address pairing apparatus for a control store of a data processi

1980-04-15

1982-09-07

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 926

Patent

active

043487246

ABSTRACT:
A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

REFERENCES:
patent: 4050058 (1977-09-01), Garlic
patent: 4058850 (1977-11-01), Sheikh

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