1991-09-11
1994-01-04
Richardson, Robert L.
395425, G06F 1200
Patent
active
052768120
ABSTRACT:
In an address multiplexing apparatus for multiplexing address data to be supplied to 64K bit, 256K bit, and 1M bit DRAMs, upon multiplexing of address data, input address data of 20 bits are classified into two groups, i.e., the lower 16 bits and the upper 4 bits. The lower 16-bit group is multiplexed so that the upper 8 bits serve as row address data, and the remaining lower 8 bits serve as column address data. In the upper 4-bit group, adjacent bits are multiplexed. The apparatus can be commonly used for the three memories having different capacities with the simple circuit arrangement, and page mode access can be executed.
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Kanuma Akira
Tamaru Kiichiro
Tanaka Koichi
Yamada Yasuo
Kabushiki Kaisha Toshiba
Richardson Robert L.
Shin C.
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