Address multiplex semiconductor memory device for enabling testi

Details Address multiplex semiconductor memory device for enabling testi Address multiplex semiconductor memory device for enabling testi

1996-02-29

1998-03-10

Nguyen, Hoa T.

Excavating

371 212, 365201, G11C 700, G11C 2900

Patent

active

057269947

ABSTRACT:
A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

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