Address memory system

Details Address memory system Address memory system

1974-10-07

1976-10-19

Wise, Edward J.

Communications: electrical

Digital comparator systems

235151, G11C 900

Patent

active

039874176

ABSTRACT:
A binary address memory unit which generates, in response to successive command inputs, successive binary output address words which progress directly according to binary count. Each command input provides for generation of time sequenced clock pulses which, in conjunction with an adder circuit, causes a next successive higher output to be generated from an output register and causes binary one to be added to that output as a stored address to be read out upon the time occurrence of a next successive input command.

REFERENCES:
patent: 3295849 (1967-01-01), Miller et al.
patent: 3310659 (1967-03-01), Apostle et al.
patent: 3375352 (1968-03-01), House et al.
patent: 3609665 (1971-09-01), Kronles et al.
patent: 3701105 (1972-10-01), Harper et al.
patent: 3718812 (1973-02-01), Tillman et al.

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