Address lookup table

Multiplex communications – Pathfinding or routing – Combined circuit switching and packet switching

Reexamination Certificate

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C370S389000, C370S392000, C370S400000

Reexamination Certificate

active

10421013

ABSTRACT:
Apparatus and method for an address lookup table is described. The address lookup table for a packet includes: an Internet Protocol field, a router port field, a router port interface field, and a Media Access Control (MAC) address field. Where the Internet Protocol field, the router port field, the router port interface field and the MAC address field have a total bit length less than or equal to sixty-four bits.

REFERENCES:
patent: 6023563 (2000-02-01), Shani
patent: 6275491 (2001-08-01), Prasad et al.
patent: 6279045 (2001-08-01), Muthujumaraswathy et al.
patent: 6430188 (2002-08-01), Kadambi et al.
patent: 6633865 (2003-10-01), Liao
patent: 6661794 (2003-12-01), Wolrich et al.
patent: 6891397 (2005-05-01), Brebner
patent: 7006526 (2006-02-01), Biederman
patent: 7116681 (2006-10-01), Hovell et al.
patent: 2002/0021703 (2002-02-01), Tsuchiya et al.
patent: 2002/0159461 (2002-10-01), Hamamoto et al.
patent: 2003/0026211 (2003-02-01), Xu et al.
patent: 2003/0108038 (2003-06-01), Devanagondi et al.
patent: 2004/0001488 (2004-01-01), Harri
patent: 2004/0264465 (2004-12-01), Dunk
patent: 2005/0243818 (2005-11-01), Foglar et al.
patent: 2006/0114908 (2006-06-01), Kalkunte et al.
U.S. Appl. No. 10/420,603, filed Apr. 21, 2003, Brebner.
U.S. Appl. No. 10/420,652, filed Apr. 21, 2003, Brebner.
Brebner, Gordon; “Mixed-Version IP Router (MIR)”, XAPP655 (v1.2), Oct. 13, 2004, pp. 1-18, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/; downloaded Apr. 18, 2003; pp. 1-6.
N. Bergmann et al.; “Reconfigurable Computing and Reactive Systems”; Proceedings of the 7th Australasian Conference on Parallel and Real-Time Systems; Springer; Nov. 29-30, 2000; pp. 171-180.
F. Braun et al.; “Reconfigurable Router Modules Using Network Protocol Wrappers”; 11th International Conference on Field Programmable Logic and Applications; Springer LNCS 2147; Aug. 27-29, 2001; pp. 254-263.
G. Brebner; “A Virtual Hardware Operating System for the Xilinx XC6200”; 6th International Workshop on Field Programmable Logic and Applications; Springer LNCS 1142; Sep. 23-25, 1996; pp. 327-336.
G. Brebner et al.; “Chip-Based Reconfigurable Task Management”; 11th International Conference on Field Programmable Logic and Applications; Springer LNCS 2147; Aug. 27-29, 2001; pp. 182-191.
G. Brebner; “Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro”; IEEE Symposium FPGAs Custom Computing Machines; IEEE Computer Society Press; Apr. 22-24, 2002; pp. 35-44.
J. Burns et al.; “A Dynamic Reconfiguration Run-Time System”; Proc. 5th Annual IEEE Symposium on FPGAs Custom Computing Machines, IEEE; Apr. 16-18, 1997; pp. 66-75.
O. Diessel et al.; “Run-Time Compaction of FPGA Designs”; 7th International Workshop on Field Programmable Logic and Applications; Springer LNCS 1304; Sep. 1-3, 1997; pp. 131-140.
H. ElGindy et al.; “Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer”; 10th International Workshop on Field Programmable Logic and Applications; Springer LNCS 1896; Aug. 27-28, 2000; pp. 379-388.
H. Fallside et al.; “Internet Connected FPL”; 10th International Workshop on Field Programmable Logic and Applications; Springer LNCS 1896; Aug. 27-30, 2000; pp. 48-57.
D. Harel; “Statecharts: A Visual Formalism for Complex Systems”; Science of Computer Programming;8; Jun. 1987; pp. 231-274; downloaded from: http://www.wisdom.weizmann.ac.iL/˜dharel/SCANNED.PAPERS/Statecharts.pdf.
A. Silberschattz et al.; “Applied Operating System Concepts”; 1st Edition; New York; published by John Wiley & Sons; Copyright 2000; Chapter 5: Threads; pp. 116-117.
G. Brebner; “Multithreading for Logic-Centric Systems”; 12th International Conference on Field Programmable Logic and Applications; Montepellier, France; Sep. 2-4, 2002; Springer LNCS 2438; pp. 5-14.
R. Gilligan et al.; Internet Requests for Comments (RFC); RFC 2893 “Transition Mechanisms for IPv6 Hosts and Routers”; Aug. 2000; Accessible at http://www.rfc-editor.org/rfc.html.
A. Conta; Internet Requests for Comments (RFC); RFC 2473 “Generic Packet Tunneling in IPv6 Specification”; Dec. 1998l Accessible at http://www.rfc-editor.org/rfc.html.
G. Tsirtsis; Internet Requests for Comments (RFC); RFC 2766 “Network Address Translation—Protocol Translation (NAT-PT)”; Feb. 2000; Accessible at http://www.rfc-editor.org/rfc.html.
E. Nordmark; Internet Requests for Comments (RFC); RFC 2765 “Stateless IP/ICMP Translation Algorithm (SIIT)”; Feb. 2000; Accessible at http://www.rfc-editor.org/rfc.html.
R. Hinden et al.; Internet Requests for Comments (RFC); RFC 2374 “An Aggregatable Global Unicast Address Format”; Jul. 1998; Accessible at http://www.rfc-editor.org/rfc.html.
G. Brebner; “Highly Reconfigurable Communication Protocol Multiplexing Element for SCOPH”; Reconfigurable Technology, Proceedings of SPIE, 4525; Aug. 21-22, 2001; pp. 99-106.
J. Lockwood et al.; “Reprogrammable Network Packet Processing on the Field Programmable Extender (FPX)”; 9th International Symposium on Field Programmable Gate Arrays; ACM Press 2001; pp. 87-93.
J. Ditmar et al.; “A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization”; Proc. 10th International Conference on Field Programmable Logic and Applications; Springer LNCS 1896; Aug. 27-30, 2000; pp. 19-28.
S. Guccione et al.; “A Reconfigurable Content Addressable Memory”; Parallel and Distributed Processing; 15 IPDPS 2000 Workshop; Springer LNCS 1800; May 1-5, 2000; pp. 882-889.
G. Brebner et al.; “Runtime Reconfigurable Routing”; Proc. 12th International Parallel Processing Symposium and 9th Symposium Parallel and Distributed Process; Springer LNCS 1388; Mar. 30-Apr. 3, 1998; pp. 25-30.
D. Comer; Chapter 22 The Future IP (IPv6) ofComputer Networks and Internets; (3rd Edition); Prentice-Hall; 2001; pp. 338-349.
A. Dollas et al.; “Architecture and Applications of PLATO: . . . ”; Proc. 9th IEEE Symposium on Field Programmable Custom Computing Machines; IEEE Press; Apr. 30-May 2, 2001; pp. [Preliminary Proceeding].
http:/ /www.npforum.org.
http:/ /www.6bone.net.
http:/ /www.xilinx.com/products/platform/.
http:/ /www.whnet.com/giga.html.
http:/ /www.chips.ibm.com/products/coreconnect/.

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