Address lines load reduction

Details Address lines load reduction Address lines load reduction

1996-06-24

1998-12-01

Sheikh, Ayaz R.

395309, 395401, G06F 1340

Patent

active

058450980

ABSTRACT:
Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

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patent: 5148539 (1992-09-01), Enomoto et al.
patent: 5235684 (1993-08-01), Becker et al.
patent: 5359717 (1994-10-01), Bolwes et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5638520 (1997-06-01), Moyer

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