Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-06-05
2007-06-05
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230080
Reexamination Certificate
active
11164723
ABSTRACT:
An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.
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patent: 6711648 (2004-03-01), Poechmueller et al.
patent: 6747909 (2004-06-01), Kang
patent: 2000-106532 (2000-04-01), None
patent: 10-1999-006349 (1999-01-01), None
Hynix / Semiconductor Inc.
Phung Anh
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