Address latch circuit of semiconductor memory device

Details Address latch circuit of semiconductor memory device Address latch circuit of semiconductor memory device

2007-03-08

2009-11-03

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100, C365S233110, C365S233120, C365S233130

Reexamination Certificate

active

07613069

ABSTRACT:
An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second address signal according to a divided clock, which is divided from an external clock, and a write latency signal, and outputs a third address signal. A second address latch part latches the third address signal according to a second address latch signal and outputs a fourth address signal.

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Notice of Patent Grant-Korean Intellectual Property Office, Jul. 23, 2007.

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