Address latch circuit of memory device

Details Address latch circuit of memory device Address latch circuit of memory device

2007-05-08

2007-05-08

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189050, C327S215000, C327S218000, C327S219000

Reexamination Certificate

active

10980350

ABSTRACT:
An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possible to reduce power consumption caused during the level transition of the address signal.

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