Address input buffer

Details Address input buffer Address input buffer

1992-04-24

1994-04-19

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523002, 36518905, 307279, G11C 1700, H03K 3286

Patent

active

053052820

ABSTRACT:
An address input buffer of a semiconductor memory device comprises an address input terminal, a column address switch, a row address switch, a column address latch connected to the column address switch, a row address latch connected to the row address switch, and an input buffer connected to the address input terminal, and the common node of the column address switch and the row address switch and controlled by an input buffer control signal. Thus, layout area can be reduced by buffering the row and column address input signals with one input buffer without separating the column and row address buffers.

REFERENCES:
patent: 4031415 (1977-06-01), Redwine et al.
patent: 5157284 (1992-10-01), O'Connell et al.
patent: 5191555 (1993-03-01), Tabacco et al.

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