Address handler for an asynchronous transfer mode switch

Multiplex communications – Wide area network – Packet switching

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370 60, H04L 1256

Patent

active

054673496

ABSTRACT:
An improved address handling circuit includes a temporary storage device for temporarily storing at least one current cell, including a header, for address processing. A virtual channel (VC) filter is coupled to the temporary storage device and includes a VC address storage device for storing at least one selected virtual channel identifier (VCI), corresponding VC matching data and a corresponding cell identifier. The VC filter compares data from the header of the at least one current cell with the selected VCI to identify cells matching the at least one VCI. The VC filter includes a VC matching device for indicating a match. A virtual path (VP) filter is coupled to the temporary storage device and includes a VP address storage device for storing at least one selected virtual path identifier (VPI), corresponding VP matching data and a corresponding cell identifier. The VP filter compares the data from the header of the at least one current cell with the selected VPI to identify cells matching the at least one VPI. The VP filter includes a VP matching device for indicating a match. The VP filter has lower priority than said VC filter. A match priority device, coupled to the VC matching device of the VC filter and to the VP matching device of the VP filters, retrieves the matching data from a highest priority filter having a match.

REFERENCES:
patent: 5163045 (1992-11-01), Caram et al.
patent: 5253251 (1993-10-01), Aramaki
patent: 5271010 (1993-12-01), Miyake et al.
patent: 5311509 (1994-05-01), Heddes et al.
patent: 5323389 (1994-06-01), Bitz et al.

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