Address generator with controllable modulo power of two addressi

Details Address generator with controllable modulo power of two addressi Address generator with controllable modulo power of two addressi

1995-06-07

1997-02-25

Ngo, Chuong D.

Boots, shoes, and leggings

39542107, G06F 738, G06F 1200

Patent

active

056065205

ABSTRACT:
A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.

REFERENCES:
patent: 4742479 (1988-05-01), Kloker et al.
patent: 4794517 (1988-12-01), Jones et al.
patent: 4833602 (1989-05-01), Levy et al.
patent: 4935867 (1990-06-01), Wang et al.

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