Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2001-05-10
2002-10-01
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S233100
Reexamination Certificate
active
06459649
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an address generator for generating addresses for an on-chip trim circuit that is used to tune reference voltages produced on a semiconductor chip.
In particular in integrated memory modules, e.g. DRAMs, voltage generators located on the chip must be adjusted or trimmed, in their target voltage, which fluctuates due to manufacturing tolerances. For the calibration, it is known to use an address generator on the chip that is connected with a trim circuit and that counts through the possible calibration stages. Electrical “fuses” are connected with an address generator of this sort, in order to permanently store the addresses generated by the address generator for the trim circuit, given agreement of the respective changing or variable reference voltage with a comparison or reference supplied externally, in that a respective electrical fuse is shot or left intact corresponding to the finally valid address information.
In general, in highly integrated semiconductor circuits, such as e.g. a 256M SDRAM, it is necessary to keep the surface required by a functional unit on the semiconductor chip as small as possible, and to reduce the number of control lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an address generator for generating addresses for an on-chip trim circuit which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the surface required by it on the semiconductor chip is optimized, the number of control lines is reduced, and, moreover, a circuit configuration is achieved that is as flexible as possible and can be adapted to various functional demands.
With the foregoing and other objects in view there is provided, in accordance with the invention, an address generator for generating addresses for a trim circuit for tuning a reference voltage produced on a semiconductor chip. The address generator contains a control input for receiving a control signal, a clock input for receiving a clock signal, and a number of M stages having memory latches and connected to the clock input and to the control input. Upon the control signal being supplied to the control input and upon the clock signal being applied to the clock input, the number of M stages are able to be operated as a synchronous counter or a shift register, where M is greater than or equal to 1.
According to an essential aspect, the inventive address generator contains a particular number of stages, each made up of a memory latch. Here each latch is realized as an edge-controlled flip-flop, as used in synchronous counters. When a clock signal is supplied to a clock input, and a control signal is supplied, the address generator can optionally be operated as a counter or as a shift register. The number of stages is at least equal to 1.
The stages of the address generator each contain one of the previously mentioned electrical fuses. Each memory latch has MOS transistors, in order to match address information that is to be supplied to the electrical fuses to the CMOS level.
The memory latches have a common initialization input and a charge or load input, and are set up in such a way that a signal applied to the charge input brings the latch information into the value complementary to the initialization value only if the respective fuses are intact (or shot depending on the technology used).
In a preferred development, the address generator can be supplemented with the following further functions. The address generator can contain a serial input and a serial output for reading out a counter state or the fuse information. The address generator can additionally contain feedback elements that optionally couple the serial output back to the serial input. Through the feedback of the serial output to the serial input, the counter state or the fuse information can be read out non-destructively at the serial output. On the other hand, other information, e.g. test information, can be applied to the serial input and can be taken over into the address generator in clock-controlled fashion. In addition, a programming input can be provided at the address generator in order to program the fuses bit-by-bit with the information present in the memory latches. Moreover, a forwards-backwards selector input can be provided for the selection of the counting direction of the counter, or the shift direction of the shift register of the address generator. The shift register of the address generator can be expanded by an additional memory latch (1 bit), in which a current (YES/NO) comparison result of a voltage comparator can be stored that compares the voltage currently produced by the trim circuit with an external reference voltage. The comparison result stored in the additional memory element can then be emitted at the serial output together with the generated address value.
Advantageously, the inventive address generator optimizes the required surface on the semiconductor chip and reduces the number of control lines. In particular, the number of output lines to an external test device is lowered to 1. In addition, the inventive address generator can be adapted in an optimal manner to various functional requirements by the optionally proposed expansions.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an address generator for generating addresses for an on-chip trim circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5886940 (1999-03-01), Morzano et al.
patent: 5889727 (1999-03-01), Hsu et al.
patent: 5892719 (1999-04-01), Kanagawa
patent: 5933370 (1999-08-01), Holzmann et al.
Krause Gunnar
Spirkl Wolfgang
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Phan Trong
Stemer Werner H.
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