Address generator for error control system

Details Address generator for error control system Address generator for error control system

1996-10-02

1998-06-30

Hua, Ly

Excavating

39518204, 371 401, 371 371, G06F 1110

Patent

active

057746486

ABSTRACT:
An address generator provided on an error control chip of an optical disk storage for addressing a plurality of working buffers accessed by a CPU, an optical disk drive (ODD), and encoder/decoder circuitry during error correction operations. The address generator comprises a loading address generator that produces an adop address signal to provide linear buffer access for the CPU and ODD when data are supplied from and to the CPU and ODD for encoding and decoding. A processing address generator produces an adex address signal that provides interleaving and random buffer access for the encoder/decoder circuitry during data encoding and decoding operations. A buffer rotation control circuit produces address and data bus control signals to provide the rotation of the buffers between the CPU, ODD, and encoder/decoder circuitry in various encoding and decoding cycles to support a pipeline error control arrangement.

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