Address generator for a semiconductor memory

Details Address generator for a semiconductor memory Address generator for a semiconductor memory

2000-08-15

2002-06-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080

Reexamination Certificate

active

06400636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor device, and in particular, to a semiconductor memory device.
2. Background of the Related Art
An address input path of a semiconductor memory is as following. Once an external address is inputted to the semiconductor memory, a complementary address signal is provided using the external address. The address signal activates a corresponding word line out of a plurality of word lines by being decoded again by an actual decoder.
FIG. 1
shows a circuit of an address signal generator in a semiconductor memory according to the related art. Referring to
FIG. 1
, a part from which an address signal is actually generated consists of NOR gates
108
and
112
and inverters
110
and
114
. In the address generating part of
FIG. 1
, an external address BXIN
0
is transformed into address signals BXT
0
and BXB
0
. The external address BXIN
0
is first inputted to an inverter
102
. Then, the address BXIN
0
is latched. A latch consists of inverters
104
and
106
.
An output of the inverter
102
is inputted to the NOR gate
112
. An output of the latch, which is the output of the inverter
104
, is inputted to the NOR gate
108
. The inverter
102
and the inverter
106
of the latch are tri-state inverters that are enabled by an address enabling signal XAEI and its inverted signal.
The inverter
102
is enabled when the address enabling signal XAEI is at low level. The inverter
106
of the latch is enabled when the address enabling signal XAEI is at high level, to latch the external address BXIN inputted through the inverter
102
. Namely, during one period of the address enabling signal XAEI, the inputting and the latching operations of the external address BXIN are completed.
An address signal generation enabling signal XAEBI is inputted to the NOR gates
108
and
112
where the address signals BXT
0
and BXB
0
are generated. A state transition of the address signal generation enabling signal XAEBI occurs sooner than that of the address enabling signal XAEI. The address signal generation enabling signal XAEBI should be at low level so that outputs of the inverter
102
and the inverter
104
of the latch are outputted as address signals BXT and BXB.
Logic gates
122
to
134
have the same structure of the above described logic gates
102
to
114
and operate the same way. Namely, they produce address signals BXT
1
and BXB
1
using another external address BXIN
1
. Additional sets of the logic gates may be added to the related art memory in accordance with the number of bits of the address.
FIG. 2
shows an address decoder in a semiconductor memory according to the related art. Referring to
FIG. 2
, a plurality of internal addresses AX are generated by combining address signals BXT and BXB, which are generated by a corresponding related art address signal generating part as shown in FIG.
1
. The internal addresses AX are used for activating word lines so that only a single signal is preferably activated out of a plurality of the internal addresses AX
0
to AXn.
In the related art address decoder, an AND gate, which consists of a NAND gate
202
and an inverter
204
, receives an address signal BX. In accordance with the combination of the address signals BX, one of the outputs (i.e., four) from the inverters, (i.e., inverter series
204
a,
204
b,
204
c,
204
d
) is activated to high level, thereby enabling a corresponding word line. An OR gate consisting of a NOR gate
206
and an inverter
208
is an output stage for an internal address. The OR gate outputs an internal address AX (i.e., AX
00
, AX
01
, AX
02
and AX
03
) generated by decoding to the word line in a normal mode. Otherwise, the OR gate selects all the word lines by fixing all the internal addresses AX to high level in a test mode. In
FIG. 2
, when a test signal TEST is on high level, an output of the NOR gates
206
(i.e., NOR gate series
206
a,
206
b,
206
c
and
206
d
) is fixed to low level and the output of inverters
208
series (i.e., AX
00
, AX
01
, AX
02
and AX
03
) become high level.
FIG. 3
is a timing diagram of operational characteristics of an address signal generator and an address decoder in a semiconductor memory according to the related art. Referring to
FIG. 3
, the address signal generation enabling signal XAEBI goes down to low level while the external address BXIN is confirmed. Then, the address enabling signal XAEI goes up to high level. In this case, logic values of address signals BXT and BXB are confirmed as soon as the address enabling signal XAEI goes up to high level because the NOR gates
108
,
112
,
128
, and
132
in
FIG. 1
were enabled by the address signal generation enabling signal XAEBI before the address enabling signal XAEI goes to high level. Further, when the address enabling signal XAEI goes to low level, the address signals BXT and BXB are fixed to high level regardless of the logic value of the external address BXIN.
The logic values of the address signals BXT and BXB are complementary to each other. In particular, BXT and BXB are at low and high levels, respectively, when the external address BXIN is at low level. Otherwise, BXT and BXB are at high and low levels, respectively, when the external address BXIN is on high level. As the address signals BXT and BXB are generated, an internal address AX is generated by the related art address decoder. When the NOR gate
206
(i.e.,
206
a
to
206
d
) in
FIG. 2
is not in test mode, an internal signal AX is generated as soon as the address signal BX is generated and free from influence of the test signal TEST as shown in FIG.
3
.
As described above, the related art address signal generator and address decoder in a semiconductor memory have various disadvantages. In particular, in the semiconductor memory of the related art, the complementary address signals BXT and BXB generated from the address signal generator are transferred to the address decoder. Then, the address decoder generates an internal address using both address signals BXT and BXB. Therefore, many signal transfer paths occur between the address decoder and the address signal generator. Moreover, the address signal BX is latched while the address input enabling signal XAEI is activated. In addition, an ineffective internal address AX may be generated by an ineffective external address BXIN since the NOR gates in the address signal generator are already enabled by the address signal generation enabling signal XAEBI. In the related art memory device, a malfunction of the memory may occur because of the selection of an incorrect address of an word line.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the invention is to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a semiconductor memory that reduces improper internal address generation by direct address signal generation in an address signal generator and decoder.
Another object of the present invention is to provide a semiconductor memory that controls signal timing to reduce improper internal address generation.
Another object of the present invention is to provide a semiconductor device that reduces or prevents ineffective internal address from being generated by reducing the signal transferring paths between an address signal generator and a decoder as well as by controlling a signal output timing.
To achieve at least these objects and other advantages in whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a semiconductor memory device having an address signal generator that produces

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