Address generator employing selective merge of two independent a

Details Address generator employing selective merge of two independent a Address generator employing selective merge of two independent a

1993-11-30

1998-01-27

Lane, Jack A.

3954211, 395516, G06F 1200, G06F 1562

Patent

active

057129991

ABSTRACT:
An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of index address registers (612) and a full adder (615). Each address unit (610, 620) selects one of the base address registers (611) and one of the index address registers (612) according to the current instruction. The full adder (615) selectively adds the index address to the base address or subtracts the index address from the base addess according to the current instruction. An address multiplexer register (630) stores an N bit multiplex word. An address multiplexer (641) selects for each bit of the merged address from the first or second N bit address depending on the state of the corresponding bit of the multiplex word: An overflow detector (631, 633) generates an overflow signal when either the first address or the second address are beyond a predetermined range. The instruction may specify generation of the address regardless of overflow detection, aborting the address generation upon overflow detection or issuing a processor interrupt upon overflow detection. In the preferred embodiment of this invention, the address unit (120) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.

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