Address generation system

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G60F 936

Patent

active

047759330

ABSTRACT:
An address generation system comprising a decoder for decoding an addressing field of a given instruction code, and a control circuit connected to the decoder to cause a register to be read out in accordance with the decoded information. A hold circuit is connected to the decoder to hold an address generation information for generating an address of an operand. A correction number generator is connected to the hold circuit to generate a correction number determined in accordance with the address generation information for the designated register. An adder is provided to receive the correction number and the content read out from the register and to output the content of the register modified by the correction number.

REFERENCES:
patent: 4197578 (1980-04-01), Wada et al.
patent: 4539635 (1985-09-01), Boddie et al.
patent: 4731736 (1988-03-01), Mothersole et al.

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