Address generation and data path arbitration to and from SRAM to

Details Address generation and data path arbitration to and from SRAM to Address generation and data path arbitration to and from SRAM to

1996-06-06

1998-10-06

Kizou, Hassan

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

370474, 3952008, G06F 1316, H04L 1256

Patent

active

058188444

ABSTRACT:
An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

REFERENCES:
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patent: 5434976 (1995-07-01), Tan et al.
patent: 5602995 (1997-02-01), Hendel et al.
patent: 5727149 (1998-03-01), Hirata et al.
patent: 5729681 (1998-03-01), Aditya et al.

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