Address generating system

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G11C 800

Patent

active

042401399

ABSTRACT:
A data processor includes a base register for a base address modification and a program counter for a relative address modification. An instruction executed in the data processor includes an operation code, a first operand, an address modification judgement bit, an index address modification field, a base address modification field and a displacement. When the instruction is fetched, it is arranged in an address modification and a base modification according to the address modification judgement bit. In the case of the relative address modification, the contents of the program counter is added to the contents of the displacement. In the case of the base address modification, the contents of the base register specified by the base address modification field is added to the contents of the displacement. In the relative address modification and the base address modification, the contents of the general register specified by the index address modification is added to the results of the addition, thereby to form an effective address.

REFERENCES:
patent: 3737867 (1973-06-01), Cavin et al.
patent: 4107774 (1978-08-01), Joyce et al.
patent: 4117536 (1978-09-01), Bodner

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