Address generating method, and circuit therefor

Details Address generating method, and circuit therefor Address generating method, and circuit therefor

1991-07-19

1994-03-22

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358460, H04N 140

Patent

active

052969380

ABSTRACT:
An address generating circuit for generating addresses capable of scanning two-dimensionally arrayed data in zigzag fashion includes an up/down counter for generating addresses in the column direction of the two-dimensional array, an up/down counter for generating addresses in the row direction of the two-dimensional array, and a circuit block for detecting, based upon a three-bit column address and a three-bit row address outputted by respective ones of the counters, whether an address is situated on an edge portion of the two-dimensional array, and for producing an up-count control signal and a down-count control signal of each counter in accordance with the results of detection. This makes it possible to generate addresses that are capable of scanning the two-dimensionally arrayed data in zigzag fashion. Also disclosed is a method of generating addresses using this circuit.

REFERENCES:
patent: 4951157 (1990-08-01), Koh et al.
patent: 4958236 (1990-09-01), Nagashima et al.
patent: 4999715 (1991-03-01), Porrellio et al.

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