Address generating mechanism for multiple virtual spaces

Details Address generating mechanism for multiple virtual spaces Address generating mechanism for multiple virtual spaces

1980-03-19

1982-10-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 936

Patent

active

043553559

ABSTRACT:
The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The invention allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data.
The embodiment obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.

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