Address generating device for a communication line scanning devi

Details Address generating device for a communication line scanning devi Address generating device for a communication line scanning devi

1982-10-12

1985-01-01

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 100

Patent

active

044919131

ABSTRACT:
The address generating device is provided for a communication line scanning device. The lines are connected to the scanning device through n line interface circuits, n varying in accordance with the network configuration. Each interface circuit can be connected to a various number of lines, for instance one line or k lines in a preferred embodiment, and comprises means for providing to the address generating device, a presence indicating signal indicating that it is plugged and a signal indicating the number of the lines connected thereto. A first logic circuit receives the presence indicating signals as inputs and generates on its outputs the address bits of the last present interface circuit to be scanned. A first counter able to count in binary mode up to n-1 is incremented by an increment pulse provided by a clock on each period assigned to the scanning of a line. This counter outputs the address bits of the successive interface circuits. A comparator compares the address bits so generated and the address bits of the last present interface circuit to be scanned and outputs a reset signal when these bits are equal.

REFERENCES:
patent: 4336588 (1982-06-01), Vernon et al.
D. Sellier "Fully Programmable Scanner" vol. 23, No. 6, Nov. 1980 pp. 2323-2324--IBM Technical Disclosure Bulletin.
S. Meguro "Automatic Module Detection" vol. 22, No. 10, Mar. 1980 pp. 4615-4616--IBM Technical Disclosure Bulletin.

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