Address generating circuit using a base pointer of loop area

Details Address generating circuit using a base pointer of loop area Address generating circuit using a base pointer of loop area

1995-02-22

1995-11-28

Lane, Jack A.

395375, 39542109, 39542108, G06F 1200

Patent

active

054716004

ABSTRACT:
An address generating circuit includes a latch circuit and two adder/subtractors. The inputs of the first adder/subtractor are from the latch circuit and from a distance relative to a value of a base pointer, and the output computes an address. The second adder/subtractor uses loop width information to adjust the computed address of the first adder/subtractor so that it falls within a loop area.

REFERENCES:
patent: 4024507 (1977-05-01), Berkling et al.
patent: 4477878 (1984-10-01), Cope
patent: 4602328 (1986-07-01), Finger et al.
patent: 4677547 (1987-06-01), Omoda et al.
patent: 5083267 (1992-01-01), Rau et al.
patent: 5150471 (1992-09-01), Tipon et al.
patent: 5155823 (1992-10-01), Tsue

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