Address generating circuit of semiconductor memory device

Details Address generating circuit of semiconductor memory device Address generating circuit of semiconductor memory device

1999-12-08

2001-03-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230020, C365S240000

Reexamination Certificate

active

06205081

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an address generating circuit of a semiconductor memory device which generates read and write addresses when the semiconductor device having read and write functions after different cycle is operated in each of normal and burst modes.
2. Description of the Prior Art
Semiconductor memory devices can be classified according to their address generating methods into normal mode and burst mode, and the burst mode is classified into linear burst mode and interleave burst mode.
In the normal mode, an address input externally is generated as an internal address when a read or write command is performed. In the burst mode, a burst starting address is input externally, and thereafter a burst continuing address is generated. In the linear burst mode, the burst continuing address increases from the burst starting address. In the interleave burst mode, the burst continuing address increases from the burst starting address if the burst starting address is an even number, and decreases from the burst starting address if the burst starting address is an odd number.
As described in the above, the conventional semiconductor memory performing the normal and burst modes and the burst counter for performing such modes are already well known.
FIG. 1
is a block diagram showing an address generating circuit of a conventional semiconductor memory device. The circuit comprises address buffers
10
and
18
, a clock buffer
26
, multiplexers
12
,
14
,
20
,
22
,
30
, counter
28
, latches
16
,
24
, and a control circuit
32
.
The operations of these blocks are now described. An external address XA is considered divided into a high left portion with n-j bits, and a low level portion, with j bits. Usually j=2.
The address buffer
10
buffers the other bit XA(n, . . . , 3) except a low 2 bit among n bit addresses XAB(n, . . . , 1), and generates the buffered addresses AB(n, . . . , 3). The address buffer
18
buffers a low 2 bit XA(2, 1), and generates the buffered address AB (2, 1). The clock buffer
26
buffers the clock signal XCLK inputted externally, and generates the buffered clock signal KIN. The multiplexers
12
,
20
allow the buffered addresses AB(n, . . . , 3), AB(2,1) to be transmitted as their output signals AAB(n, . . . , 3), AAB(2,1), in response to the buffered clock signal KIN.
The control circuit
32
receives an inversion chip selective signal CSB, a read/write control signal GWB, a normal/burst mode control signal ADVB, and the buffered clock signal KIN to generate an external input control signal KEXT, an external input selective signal PEXT, a burst continuing control signal KBURST, and a burst input selective signal PBURST. A chip is enabled when the inversion chip selective signal CSB is at a low level, a write command is performed when the read/write control signal GWB is at a low level, a read command is performed when the read/write control signal GWB is at a high level, and a burst address of burst mode is generated when the normal/burst mode control signal ADVB is at a high level. The control signal KEXT is generated prior to selective signal PEXT, to generate the burst starting address. The burst continuing control signal KBURST is generated a predetermined time before the burst input selective signal PBURST is generated, to generate the burst continuing address.
The counter
28
receives and outputs the output signal AA(2, 1) in response to the control signal KEXT when it is at a normal mode, and receives and outputs the burst starting address outputted from the multiplexer
20
in response to control signal KEXT when it is at a burst mode, and performs counting at the burst starting address in response to the burst continuing control signal KBURST to generate the burst continuing address as an output signal CAB(2,1).
The multiplexers
14
,
22
generate the output signals AAB(n, . . . , 3) and AAB(2,1) of the multiplexers
12
,
20
in response to the external input selective signal PEXT, respectively. The multiplexer
30
elects and outputs the output signal CAB(2, 1) of the counter
28
in response to the burst input selective signal PBURST. The latch
16
latches and outputs the output signal of the multiplexer
14
. The latch
24
latches and outputs the output signal of the multiplexer
22
, or multiplexer
30
. The latched addresses are outputted to a decoder and decoded by it.
The counter
28
shown in
FIG. 1
generates the burst continuing address in accordance with the processes as stated in the above, in case of a linear burst mode and in case of an interleave burst mode, respectively.
In
FIG. 1
, the route or data path consisting of address buffer
10
, multiplexers
12
and
14
, latches
16
and the route consisting of address buffer
18
, multiplexers
20
,
22
, latch
24
are for generating read and write addresses in a normal mode. The route consisting of address buffer
18
, multiplexer
20
, counter
28
, multiplexer
30
, latch
24
is for generating read and write addresses in a burst mode.
FIG. 2
is an operational timing diagram illustrating a burst mode operation in an address generating circuit of the conventional semiconductor memory device.
FIG. 2
shows read and write operations after 0 cycle. The operation will be explained as follows.
The first cycle I to the fourth cycle IV is for illustrating the generation of the burst write address. In the first cycle I, the control circuit
32
serves to generate the external input control signal KEXT of high level, the burst continuing control signal KBURST of low level, the external input selective signal PEXT, and the burst input selective signal PBURST in response to the inversion chip selective signal CSB of low level, read/write control signal GWB, and the normal/burst mode control signal ADVB of high level, respectively. The selective signal PEXT and the burst input selective signal PBURST are pulse signals resulting from the delay of the external input control signal KEXT and the burst continuing control signal KBURST, respectively.
The multiplexers
12
,
20
select and output the buffered addresses AB(n,*,3), AB(2,1) outputted from the address buffers
10
,
18
, in response to the buffered clock signal KIN. The counter
28
receives the burst starting write address outputted from the multiplexer
20
in response to the external input control signal KEXT, to output the output address CAB(2, 1). The multiplexer
14
selects and outputs the address AAB(n, . . . , 3) outputted from the multiplexer
12
in response to the external input selective signal PEXT. The multiplexer
30
selects and outputs the address CAB(2,1) outputted from the counter
28
in response to the burst input selective signal PBURST. The latches
16
,
24
serves to latch the address outputted from the multiplexers
14
,
30
to thereafter generate the burst starting write address.
The second cycle II to the fourth cycle IV respectively performs the repeated operation. The control circuit
32
receives the normal/burst mode control signal ADVB of “high” level to generate the external input control signal KEXT of low level and the burst continuing control signal KBURST of “high” level irrespective of the read/write control signal GWB and the inversion chip selective signal CSB. The counter
28
counts the output signal of the multiplexer
20
in response to the burst continuing control signal KBURST in response to the burst continuing control signal KBURST to thereby generate the counted output signal CAB(2,1). The multiplexer
30
selects and generate the counted output signal CAB(2,1) in response to the burst input selective signal PBURST. The latch
24
latches and outputs the output signal of the multiplexer
30
. The latch
16
outputs the address latched in the prior cycle. That is, the burst continuing write address counted from the burst starting address is generated in the second cycle to the fourth cycle.
The fifth cycle V to the eighth cycle VIII show illustra

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