Address generating circuit of a two-dimensional coding table

Details Address generating circuit of a two-dimensional coding table Address generating circuit of a two-dimensional coding table

1994-02-01

1996-09-03

Lane, Jack A.

395114, 395888, G06F 1200

Patent

active

055532578

ABSTRACT:
An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S<P and P is a positive integer); comparators which examine whether the inputted y satisfies x+log.sub.2 y.ltoreq.P for each integral number of x, and examine whether the inputted x satisfies y+log.sub.2 x.ltoreq.P for each integral number of y; an escape signal generation section which outputs an escape signal according to the output of the coincidence detectors and the comparators; an address generation section which generates and outputs an address signal from values x and y and an identification address for identifying that x and y are integers; a priority control section which inputs the output from the coincidence detectors, determines which signal is outputted with precedence and outputs it; and a multiplexer which selects and outputs an address signal in accordance with the output from the priority control section.

REFERENCES:
patent: 4545032 (1995-10-01), Mak
patent: 5280361 (1994-01-01), Ishikawa
patent: 5296938 (1994-03-01), Nakayama

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