Address generating circuit for data compression

Details Address generating circuit for data compression Address generating circuit for data compression

1993-06-08

1996-07-09

Lane, Jack A.

Excavating

371 211, G06F 1120

Patent

active

055353533

ABSTRACT:
An address generating circuit for data compression includes an X-address generating circuit (10), a Y-address generating circuit (20), an XY-address generation control circuit (30) and a defect analyzing memory (40). Each of the circuits (10) and (20) include a flip-flop (3A), a selector (2), an upcounter (4), an adder (5), a down-counter (6) and a comparator (1). The control circuit (30) receives address end signals J and address carry signals L from the circuits (10) and (20) to control the circuits (10) and (20). The memory (40) has address signals K from the circuits (10) and (20). Processing time required to check defects of a large capacity memory device is reduced because address generators are provided not only on the X-address side but also on the Y-address side and the compression ratio is set in the address generating circuit, thereby accelerating the defect analysis.

REFERENCES:
patent: 4628509 (1986-12-01), Kawaguchi
patent: 4965751 (1990-10-01), Thayer et al.
patent: 5396607 (1995-03-01), Shimatani

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