Address generating circuit

Details Address generating circuit Address generating circuit

1988-04-21

1990-02-13

Fleming, Michael R.

Excavating

371 378, G06F 1110

Patent

active

049013181

ABSTRACT:
An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The reading address is obtainable based on a formula RDA=H+2L+p, where H is a starting address of one block not inluding synchronous signal or pattern, L is a symbolic location of a symbol, and p is a sign for designating that the symbol is included in a LSB byte plane or an MSB byte plane. A first full adder (25) generates the symbolic location L based on the parameter i and j with various constants being given from a constant generator (23) so as to give the symbolic location L to a second full adder (21). The starting address H is given from a writing address pointer (12a). The second full adder adds H, 2L and p to apply the reading address to an address bus. In addition, the symbolic location L is latched in a symbol off-set address (26) and, if necessary, fed-back to the first full adder through multiplexers (24, 27) when the next symbolic location is to be generated.

REFERENCES:
patent: 4672614 (1987-06-01), Yoshida
patent: 4710934 (1987-12-01), Traynor
patent: 4715036 (1987-12-01), Oakos
patent: 4775978 (1988-10-01), Hartness
patent: 4788685 (1988-11-01), Sako

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