Address generating and decoding device and method with increased

Details Address generating and decoding device and method with increased Address generating and decoding device and method with increased

1995-03-09

1996-12-17

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

326106, 326108, G11C 800

Patent

active

055860796

ABSTRACT:
An address generator generates a binary coded address signal consisting of a combination of bit-representative low swing complementary signals. The coded address signal is decoded by an address decoder in a concurrently amplifying manner to obtain a decoded address signal consisting of a combination of symbol-representative full swing signal pairs of logical signals. The decoder comprises a binary tree of sense amplifiers each serving for outputting a logical product of an input enable signal and a corresponding low swing complementary signal, so that a single logical signal has a high level at the output end of the decoder. The high level logical signal is employed to drive a word line for an access to an arbitrary location defined in a given memory or to a desired piece of data stored therein, at an address represented by the decoded address signal.

REFERENCES:
patent: 5331219 (1994-07-01), Nakamura
patent: 5359553 (1994-10-01), Shiomi

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