Address generating and decoding apparatus with high operation sp

Details Address generating and decoding apparatus with high operation sp Address generating and decoding apparatus with high operation sp

1994-12-20

1995-11-14

Fears, Terrell W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, G11C 1300

Patent

active

054673186

ABSTRACT:
In an apparatus for adding first and second addresses to generate a third address and decoding the third address to generate a plurality of partial decoding signals, a plurality of partial decoding signal generating units, each for generating one of the partial decoding signals, are connected in parallel. Each of the partial decoding signal generating units includes an adder for adding a part of the first address to a part of the second address, a carry look ahead circuit, a decoder for decoding the output of the adder, and a shifter for shifting the partial decoding signal of the decoder. A carry output signal of one of the partial decoding signal generating units on the downstream side is supplied to the carry look ahead circuit and the shifter of another of the partial decoding signal generating units on the upstream side.

REFERENCES:
patent: 5193071 (1993-03-01), Umina et al.

Affiliated with

Also associated with

Rating

Address generating and decoding apparatus with high operation sp does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address generating and decoding apparatus with high operation sp, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address generating and decoding apparatus with high operation sp will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1225995